Modular reduction with step-by-step using of several bits of the reducible number

Although public key cryptography is known to solve the problem of physically secure exchange, main drawback this system its low performance during encrypting and decrypting data. One ways issue increase speed modular reduction operation, one basic operations asymmetric cryptoalgorithms. A new method step-by-step by N-bit module P using several bits 2Nbit reducible number in step proposed paper. The based on multiples reducing modulo at each not entire initial number, but parts (A1, A2… Ai), which allows reduce bit capacity A. structural diagram hardware implementation are developed. unit device a block partial remainder formers, computed P. circuits modeled Vivado Design Suite computer aided design (CAD) base Artix-7 Fieldprogrammable gate array (FPGA) from Xilinx. Optimization costs achieved applying same comparison compare different with Ai